As is well known, an abiding demand exists from the trade for semiconductor devices that can be operated at increasingly low supply voltages and large bandwidths.
The output buffers are a major design constraint in such devices. The desire is that such buffers output data at a very high rate despite being supplied a reduced voltage.
The problems encountered in the design of output buffer devices are intensified particular with devices that have a low internal supply voltage, while the supply voltage to the output buffers is still lower.
Shown schematically in FIG. 1 is a typical structure of an output buffer device 1. In particular, the output buffer device 1 comprises a complementary pair of CMOS transistors M1, M2 which are connected in series together between a supply voltage reference Vcc and a second voltage reference, specifically a ground reference GND, and have control terminals connected together and to an input terminal IN of the output buffer device 1, the latter being a voltage input signal Vin.
The passage from a logic low to a logic high, referred to as a low/high transition, of an output voltage signal Vpad at an output terminal PAD is effected in two steps, as specified herein below. 1. When Vpad&lt;.vertline.Vtp.vertline., the PMOS transistor M1 is in a saturated condition, and the charge current Ic which raises the value of the voltage Vpad at the output terminal PAD is constant and given approximately as: ##EQU1##
where:
Kp=.mu..multidot.Cox, PA1 1/Zp=W/L (geometric parameters of PMOS transistor M1), PA1 Vtp is the threshold voltage of PMOS transistor M1, PA1 .mu. is the electron mobility, and PA1 Cox is the capacitance of the silicon layer of the transistors.
2. When Vpad&gt;.vertline.Vtp.vertline., the PMOS transistor M1 is in the triode range, and the charge current Ic is dependent on the voltage Vpad presented at the output terminal PAD, it being given as: ##EQU2##
It appears from formulae (1) and (2) above that the charge current Ic is "quadratically" proportional to the supply voltage Vcc. With low supply voltages, large geometries (small values of Zp) must be used to provide the required fast transfer of the output data.
A state-of-art buffer device is disclosed for a supply voltage of 1.5V in U.S. Pat. No. 5,903,500 to Tsang et al. This document is related in particular to flash memories, and describes a high-speed output buffer device, which comprises a high-transconductance NMOS transistor suitably doped to have a lower threshold voltage than the threshold voltage of standard NMOS transistors.
The underlying technical problem of this invention is to provide an output buffer device for low supply voltage devices, which has such structural and functional features that it can overcome the constraints of comparable prior devices.